FIG. 1 is a block diagram showing a configuration of a conventional acoustic signal processor 1. The acoustic signal from an acoustic reproducing apparatus which is fed from an input terminal 3 and is converted into a digital value in an analog/digital converter 4 is applied in a digital signal processor 5 which is realized, for example, by a large scale integration circuit, and is subjected to arithmetic processing such as tone control. The acoustic signal data from the analog/digital converter 4 is fixed decimal point data, as shown in FIG. 2 (1), composed of a total of 32 bits, 16 bits each for right and left channels, per sampling period. In the digital signal processor 5, this 32-bit fixed decimal point data is converted into floating decimal point data of total 40 bits total as shown in FIG. 2 (2), composed of a 16-bit, mantissa portion (the portion a as expressed in the formula a.times.2.sup.b) and 4-bit exponent portion (portion b in the above formula) for each of the right and left channels per sampling period in order to enhance the dynamic range or S/N ratio. This floating decimal point data is transferred to a digital signal processor 7 through line 6 for another arithmetic processing. In this digital signal processor 7, the acoustic signal is converted again into fixed decimal point data of 32 bits per sampling period, and is delivered from an output terminal 10 by way of a digital/analog converter 9.
In such acoustic signal processing, at the analog/digital converter 4 and digital/analog converter 9, 32-bit data is processed per sampling period, and at the digital signal processors 5 and 7, 40-bit data processing is carried out. Accordingly, in the analog/digital converter 4 and digital/analog converter 9, and in the digital signal processors 5 and 7, it is necessary to install respective clock signal generators 11 and 12, corresponding to the number of bits to be processed per sampling period, and the structure is thus complicated.
In other prior art, hence, two bit number converters are provided, and the 32-bit fixed decimal point data is converted into 40-bit floating decimal point data at the input side of the digital signal processor in the front stage, while the 40-bit floating decimal point data is converted into 32-bit fixed decimal point data at the output side of the digital signal processor in the rear stage, thereby selecting the clock ,frequency so as to generate 40 pulses per sampling period, and processing on the basis of the clock pulses from one clock generator.
In this conventional example, however, the bit number converting circuit is needed, and the structure thus cannot be simplified.
It is hence a primary object of the invention to present a data transfer apparatus and system which is simplified in structure, capable of arithmetically processing and transferring fixed decimal point data and floating decimal point data differing in the number of bits on the basis of a common clock signal.
It is another object of the invention to present a data transfer apparatus for eliminating unnecessary structure, reducing cost, and realizing advanced data processing, by setting up a different structure for transfer of fixed decimal point data, when transferring fixed decimal point data, by using the register for exponent portion transfer in the floating decimal point data.
It is a different object of the invention to present a data transfer apparatus capable of using effectively the register for mantissa portion transfer and the register for exponent portion transfer in floating decimal point data, for processing of floating decimal point data and fixed decimal point data, by setting these registers in the same bit length.
It is a further different object of the invention to present a data transfer apparatus capable of arithmetically processing and transferring on the basis of a common clock signal, without using particular converting circuitry, and without deteriorating the precision, if the bit length of the mantissa portion in the floating decimal point data to be arithmetically processed is longer than the bit length of the fixed decimal point data handled externally.